By Gurpur M. Prabhu

This tutorial is intended as a supplementary learning tool for students of Com S 321, an undergraduate course on computer architecture taught at Iowa State University. The text book for the course is "Computer Organization and Design: The Hardware/Software Interface" by Hennessy and Patterson. The concepts explained include some aspects of computer performance, cache design, and pipelining.  Examples, interactive applets, and some problems with solutions are used to illustrate basic ideas. Most of the material has been developed from the text book as well as from "Computer Architecture: A Quantitative Approach" by the same authors. The problems that have been solved have been taken from a number of sources, but the solutions are unique in the sense that emphasis has been placed not only on the answers but also on the reasoning processes that will help students solve similar problems.

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Feedback consisting of comments and errors are welcome, and can be e-mailed to Gurpur Prabhu at


bullet Computer Performance 

bullet Memory Hierarchy Design