Instruction fetch cycle (IF)
Instruction decode/register fetch (ID)
Execution/Effective address cycle (EX)
Memory access/branch completion cycle (MEM)
Write-back cycle (WB)
You can see what is done on each cycle using the following applet. Selecting "all cycles" will process the whole instruction from IF to WB cycle ("Cycle" is disabled in this case and has no effect). If it appears like nothing has changed on the picture it means that the cycle is not active for the instruction type.
Detailed description of each follows:
Instruction fetch cycle (IF):
IR <- MEM[PC]Operation:
NPC <- PC +4
Instruction decode/register fetch (ID):
A <- Regs[IR6..10]Operation:
B <- Regs[IR11..15]
Imm <- ((IR16)16##IR16..31)
Execution/Effective address cycle (EX):
The ALU operates on the operand prepared in the prior cycle, performing one of four functions depending on the DLX instruction type
Memory reference:Memory access/branch completion cycle (MEM):ALUOutput <- A +ImmOperation: The ALU adds the operands to form the effective address and places the result into the register ALUOutput
Register-Register ALU instruction:ALUOutput <- A op BOperation: The ALU performs the operation specified by the opcode on the value in register A and on the value in register B. The result is placed in the register ALUOutput.
Register- Immediate ALU instruction:ALUOutput <- A op ImmOperation: The ALU performs the operation specified by the opcode on the value in register A and on the value in register Imm. The result is placed in the register ALUOutput.
Branch:ALUOutput <- NPC + ImmOperation:
Cond <- ( A op 0 )
-The ALU adds the NPC to the sign-extended immediate value in Imm to compute the address of the branch target.
-Register A, which has been read in the prior cycle, is checked to determine whether the branch is taken.
- the comparison operation op is the relational operator determined by the branch opcode (e.g. op is "==" for the instruction BEQZ)
Memory reference:Write-back cycle (WB):LMD <- Mem[ALUOutput] or Mem[ALUOutput] <- BOperation:
-Access memory if needed
- If the instruction is load , data returns from memory and is placed in the LMD (load memory data) register
- If the instruction is store, data from the B register is written into memory.
- In either case the address used is the one computed during the prior cycle and stored in the register ALUOutput
Branch:if (cond) PC <- ALUOutputOperation:
else PC <- NPC
- If the instruction branches, the PC is replaced with branch destination address in the register ALUOutput
- Otherwise, PC is replaced with the incremented PC in the register NPC
Register-Register ALU instruction:Regs[IR16..20] <- ALUOutputRegister-Immediate ALU instruction:Regs[IR11..15] <- ALUOutputLoad instruction:Regs[IR11..15] <- LMDOperation:
- Write the result into the register file, whether it comes from the memory(LMD) or from ALU (ALUOutput)
- the register destination field is in one of two positions depending on the opcode